Very large scale integrated (VLSI) circuits, such as microprocessors, require low power dissipation logic gates to avoid excessive power dissipation in the overall circuit. However, the power dissipation and switching delays are coupled according to their product, the power-delay product, which is set mainly by device (i.e. feature) size and voltage swing. Current VLSI MOSFET (metal-oxide-semiconductor field-effect transistor) devices typically operate at about 5 volts, and for about 1 .mu.m feature sizes the power-delay product is about 100 femtojoule (1 femtojoule=10.sup.-15 joule). This, combined with power dissipation of about 1 .mu.W (microwatt) per device, limits switching delays to greater than about 10 nsec. (nanoseconds). Alternatively, MOSFETs can be designed to produce approximately 50 psec. (picosecond) delays, but the power dissipation increases to about 1 mW per device. Such a dissipation value is too high to make feasible the large number of devices needed in VLSI circuits.
There is a need for a switching device that can operate simultaneously at high speed (e.g.&lt;1 nsec) and low power (e.g..ltoreq.1 .mu.W), corresponding to a .ltoreq.1 femtojoule power delay product. Since feature sizes are approaching basic limits on minimum size, such a reduction in power-delay product can be achieved only by greatly reducing voltage swings. However, rather stringent practical limits on voltage swings in current VLSI MOSFET devices and operation at room temperature prevent the use of such low voltages.